Program and Schedule

Conference Program


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Overview

Schedule
LASCAS
IBERCHIP
PRIME


Schedule


Monday 20th Tuesday Feb 21st Wednesday Feb 22nd Thursday Feb 23rd

Room Room Room Room
Time Quintral Amancay Condor Quintral Amancay Condor Quintral Amancay Condor Quintral Amancay
8:00

Registration





8:30
9:00 Registration Keynote Jie Chen

Keynote Albert Wang Keynote Víctor Grimblatt
9:30
10:00 Async. Circuit Design and Test Why FinFETs, Why 3D ICs - are we ready for tech. rev.? Coffee Coffee Coffee
10:30 LASCAS Modelling Iberchip
Digital Design
Prime Analog Design LASCAS
Special Session Resistive Memories
LASCAS
Analog Design 1
Prime
Devices and Digital Design
LASCAS
RF & communications
LASCAS Algorithms Iberchip
Analog Design
11:00
11:30
12:00 Lunch (lobby)
12:30 Lunch (hotel restaurant) Lunch (hotel restaurant) Lunch (hotel restaurant)
13:00 continues continues
13:30 e-Commerce
(Spanish)
Soft and Permanent Errors in Digital Cameras Designing a FINFET based embedded SRAM Array LASCAS Digital Design 1 LASCAS Power Electronics Iberchip
FPGA and HDL
LASCAS
Analog Design 2
LASCAS
FPGA
Iberchip Process variations - ReRAM
14:00 Coffee
14:30 PDK Generation Memristor Device Modeling and Applications in Memory, Logic, Computing and Learning
15:00 Coffee Demo L - An Ref
15:30
Industry Session CASS Meeting Coffee Coffee
16:00 Coffee LASCAS
Sensors and detection
LASCAS Fault Tolerant Systems and Rad. Eff. Iberchip
Digital Design
LASCAS Biomedical LASCAS Digital 2 LASCAS ctrl & mod
16:30 PDK Generation Eng. of Nanobiotech-nological Systems
17:00 EDA in Region Closing ceremony

17:30
18:00
18:30 Welcome reception (INVAP EMTECH) Wine taste (Synopsys) Live Demo
Tango lessons
Asado
(gala dinner)
Depart 18:30 from hotel lobby



19:00


22:00








Paper Presentations: LASCAS

Number Title Room Session Day Time
116 Improving a MOSFET Model for Design by Hand Condor Modelling Tuesday 21st 10:30
58 Asymmetrical Length Biasing for Energy Efficient Digital Circuits Condor Tuesday 21st 10:50
165 Adherence of a High-Speed RRP LDMOS Characterization Setup to JESD 24-10 Standard Condor Tuesday 21st 11:10
10 Oscillation-Based Test in a CCII-based Bandpass Filters Condor Tuesday 21st 11:30
114 Statistical Library Characterization Using Arbitrary Polynomial Chaos Condor Tuesday 21st 11:50
139 Low Power Sum of Absolute Differences Architecture Using Novel Hybrid Adder Condor Tuesday 21st 12:10
200 High Density Emerging Resistive Memories: What are the Limits? Condor Resistive Memories Wednesday 22nd 10:30
201 Studies of Dynamics of Memristor-baased Memory Cells Condor Wednesday 22nd 10:50
202 Analog memristive and memcapacitive properties of Ti / Al2O3 / Nb2O5 / Ti resistive switches Condor Wednesday 22nd 11:10
203 Optimization Opportunities in RRAM-based FPGA Architectures Condor Wednesday 22nd 11:30
102 High-Frequency Memristive Synapses Condor Wednesday 22nd 11:50
15 Exploring the Voltage Divider Approach for Accurate Memristor State Tuning Condor Wednesday 22nd 12:10
55 A 28GHz Self-Contained Power Amplifier for 5G applications in 28nm FD-SOI CMOS Quintral Analog Design 1 Wednesday 22nd 10:30
24 A versatile, CMOS compatible, integrated antenna for millimeter-wave applications Quintral Wednesday 22nd 10:50
120 Blind range level shifters from 0 to 18V Quintral Wednesday 22nd 11:10
135 A 4uA Wireless Platform for Cattle Heat Detection. Quintral Wednesday 22nd 11:30
161 A 90\% Efficiency 60 mW MPPT Switched Capacitor DC - DC Converter for Photovoltaic Energy Harvesting Aiming for IoT Applications Quintral Wednesday 22nd 11:50
18 Biased capacitive divider electrostatic generators for energy harvesting Quintral Wednesday 22nd 12:10
45 Hardware Implementation for Permutation Function of Multiplication-Hardened Sponge BlaMka Condor Digital Desing 1 Wednesday 22nd 13:30
173 A Comparison of Asynchronous QDI Templates Using Static Logic Condor Wednesday 22nd 13:50
42 Co-design System for Template Matching using Dedicated Co-processor and Particle Swarm Optimization Condor Wednesday 22nd 14:10
26 Evaluation of the uModel Factory Software Used For the Modeling of Embedded Systems with Concurrent States Condor Wednesday 22nd 14:30
4 4D reverberator-based digital filters Condor Wednesday 22nd 14:50
51 Periphery V$_{DD}$ Collapse mode in SRAMs to allow switching off Periphery Voltage Island instead of doing it per memory Condor Wednesday 22nd 15:10
7 Designing an Optimum Non-Dissipative LC Snubber for Step-Up Flyback Converters in DCM Quintral Power Electronics Wednesday 22nd 13:30
150 Coexistence of Solutions in a Boost-Flyback Converter with current mode control Quintral Wednesday 22nd 13:50
137 An small-signal averaged model of a coupled-inductor boost converter Quintral Wednesday 22nd 14:10
49 Comparative Topology and Power Loss Study for High Power Density and High Conversion Ratio Integrated Switching Power Converters Quintral Wednesday 22nd 14:30
117 Reconfigurable Multiple-Gain Active-Rectifier for Maximum Efficiency Point Traking in WPT Quintral Wednesday 22nd 14:50
172 Design of Experiments Implementation towards Optimization of Power Distribution Networks Quintral Wednesday 22nd 15:10
61 Silicon Photo-multipliers Characterization System Condor Sensors and detection Wednesday 22nd 16:00
159 Aspects on the shape dependence with energy of point-like events in high resistivity CCDs Condor Wednesday 22nd 16:20
118 Bearings-only aerial shooter localization using a microphone array mounted on a drone Condor Wednesday 22nd 16:40
89 RISC-V based ASP sound classifier intended for acoustic surveillance in protected natural environments Condor Wednesday 22nd 17:00
50 Real-time Teleoperation with the Baxter Robot and the Kinect Sensor Condor Wednesday 22nd 17:20
9 A Low-Power, High-Accuracy Capacitance-to-Time Converter for Differential Capacitive Sensors Condor Wednesday 22nd 17:40
62 Process and Temperature Impact on Single-Event Transients in 28nm FDSOI CMOS Quintral Fault Tolerant Systems and Radiation Effects Wednesday 22nd 16:00
98 Radiation Sensitivity of XOR Topologies in Multigate Technologies under Voltage Variability Quintral Wednesday 22nd 16:20
90 Evaluation of Multiple Bit Upset Tolerant Codes for NoCs Buffering Quintral Wednesday 22nd 16:40
70 Evaluating the Efficiency of using TMR in the High-Level Synthesis Design Flow of SRAM-based FPGA Quintral Wednesday 22nd 17:00
63 Applying Lockstep in Dual-Core ARM Cortex-A9 to Mitigate Radiation-induced Soft Errors Quintral Wednesday 22nd 17:20
146 Low Cost Rollback to Improve Fault-Tolerance in VLSI Circuits Quintral Wednesday 22nd 17:40
129 A high IP3 6.5 mW self-biased 0.3 - 3 GHz small area LNA Condor RF and Comunications Thursday 23rd 10:30
17 Object identification using VSWR evaluation based on a narrowband microstrip antenna and a tuned amplifier Condor Thursday 23rd 10:50
33 A 4-Wire Interface SoC for Shared Multi-Implant Power Transfer and Full-duplex Communication Condor Thursday 23rd 11:10
131 Double Quadrature Bandpass Sampling for a PLL and Mixer-less Low-IF Multistandard Receiver Condor Thursday 23rd 11:30
29 Enhancing I2C Robustness to Soft Errors Condor Thursday 23rd 11:50
157 All digital reconfigurable IR-UWB pulse generator using BPSK modulation in 130nm RF-CMOS process Condor Thursday 23rd 12:10
122 A Comparison of Four PDE-Spatial Denoising Systems for Molecular Images Quintral Algorithms Thursday 23rd 10:30
169 Exploiting Addition Schemes for the Improvement of Optimized Radix-2 and Radix-4 FFT Butterflies Quintral Thursday 23rd 10:50
95 Filtered-x Error Coded Affine Projection Algorithm with Evolving Order for Active Noise Control Quintral Thursday 23rd 11:10
53 Design of Residue Generators with CLA/Compressor Trees and Multi-Bit EAC Quintral Thursday 23rd 11:30
158 Characterizing Energy Consumption in Software HEVC Encoders: HM vs x265 Quintral Thursday 23rd 11:50
133 Energy Evaluation of the HEVC Decoding for Different Encoding Configurations Quintral Thursday 23rd 12:10
6 Calibration-Less Nauta OTA Operating at 0.25-V Power Supply in a 130-nm Digital CMOS Process Condor Analog Design 2 Thursday 23rd 13:30
40 Settling time-based Design of a Fully Differential OTA for a SC Integrator Condor Thursday 23rd 13:50
19 A Switched-Capacitor Filter with Dynamic Switching Bias OP Amplifiers Condor Thursday 23rd 14:10
94 Efficient use of Gain-bandwidth product in active filters: Gm-C and Active-R alternatives Condor Thursday 23rd 14:30
35 A 0.45 V, 93 pW Temperature-Compensated CMOS Voltage Reference Condor Thursday 23rd 14:50
125 A 2.2 uW analog front-end for multichannel neural recording Condor Thursday 23rd 15:10
83 HW/SW Codesign of Maximum Lyapunov Exponent Estimator Quintral FPGA and HDL Thursday 23rd 13:30
77 Fixed-point FPGA Implementation and Optimization for Henon Map Chaotic Generators Design Quintral Thursday 23rd 13:50
99 Approximate Frequent Itemsets Mining on Data Streams Using Hashing and Lexicographic Order in Hardware Quintral Thursday 23rd 14:10
156 A compact FPGA-based microcoded coprocessor for exponentiation in asymmetric encryption Quintral Thursday 23rd 14:30
87 Nonrecursive Comb-Based Structure for Power of Three Decimation Factors: Design and FPGA Implementation Quintral Thursday 23rd 14:50
119 FPGA Implementation of a Feedforward Neural Network-Based Classifier Using the xQuant Technique Quintral Thursday 23rd 15:10
85 Gold-Copper-Based Biosensor for Impedance Analysis of Mammalian Adherent cells Condor Biomedical Thursday 23rd 16:00
86 A Chopped Front-End System with Common-Mode Feedback for real time ECG applications Condor Thursday 23rd 16:20
138 Portable Electromagnetic Field Applicator for Magnetic Hyperthermia Experiments Condor Thursday 23rd 16:40
96 A Study of Characterizing Crosstalk Effects in 3-D Vias Quintral Digital Digital Design 2 Thursday 23rd 16:00
174 A System-on-Chip Platform for the Internet of Things featuring a 32-bit RISC-V based Microcontroller Quintral Thursday 23rd 16:20
171 Thought Vectors and Spiking Neuron Circuits Amancay Control and modeling Thursday 23rd 16:00
71 Electrical Evaluation of Adder Circuits Using Independent Gate FinFET Amancay Thursday 23rd 16:20
140 Closed Loop Frequency Control for an Hyperthermia Magnetic Field Applicator Amancay Thursday 23rd 16:40

Paper Presentations: IBERCHIP

Number Title Room Session Day Time
9 The Design of Low-Power Transition-Signaling Asynchronous Pipelines Quintral Digital Design Tuesday 21st 10:30
11 A Low-Latency Asynchronous Wrapper for GALS Systems Design Quintral Tuesday 21st 10:50
26 AMBA-AHB Network Interface for Core Interconnection in a Network-on-Chip Quintral Tuesday 21st 11:10
29 Projeto de Portas Lógicas XOR com Redução de Potência por Voltage Scaling Quintral Tuesday 21st 11:30
13 Identificação de custos computacionais causados por contadores de desempenho Quintral Tuesday 21st 11:50
25 Desempenho de Sistemas Multiagentes em Processadores Multicore Quintral Tuesday 21st 12:10
35 UFRGSPlace: Routability Driven FPGA Placement Algorithm for Heterogeneous FPGAs Amancay FPGA and HDL Wednesday 22nd 13:50
6 Análise de Metodologias de Implementação e Desempenho em FPGA dos Algoritmos Criptográficos Leves Simon, Speck e Simeck Amancay Wednesday 22nd 14:10
33 Synthesis of Auto-Synchronous FSMs from Synchronous Specification using FPGAs Amancay Wednesday 22nd 14:30
23 Sistema supervisor de constantes vitales biomédicas utilizando hardware reconfigurable Amancay Wednesday 22nd 14:50
17 A Module for Remote Reconfiguration of FPGAs in Satellites Amancay Wednesday 22nd 15:10
10 Comparison between Direct and Indirect Learning for the Identification of Digital Baseband Predistorters Amancay Digital Desgin Wednesday 22nd 16:00
12 Frequency-domain Polynomial Filter for Crest Factor Reduction in Wireless Transmitters Amancay Wednesday 22nd 16:20
22 OTG: A Target Specification for Design of Synchronous Digital Systems in the RTL Style Amancay Wednesday 22nd 16:40
19 Evolu\c{c}\~ao de BBDs aplicados a Fault Collapsing Amancay Wednesday 22nd 17:00
14 Desarrollo de un Sistema de Control inalámbrico Centralizado, orientado a la Inmótica Amancay Wednesday 22nd 17:20
36 Design and Development of Transcutaneous Electrical Stimulation Prototype for Neuromuscular Rehabilitation in Individuals with Facial Palsy Amancay Wednesday 22nd 17:40
24 An 130nm CMOS Sample-and-Hold dedicated to Double Quadrature BPS Receiver Architecture. Amancay Analog Design Thursday 23rd 10:30
5 A CMOS 0.18$\mu$m Calibrated Gain Amplifier with DC Offset Cancellation Technique for very low starting band frequency Amancay Thursday 23rd 10:50
30 Voltage-to-Frequency Converter Design for System-on-Chip Testing in 0.35m CMOS Technology Amancay Thursday 23rd 11:10
1 A Combined Memory and Envelope-Memory Polynomial Model for RF Power Amplifiers Amancay Thursday 23rd 11:30
32 A Functional Verification Method for an All-Digital Automatic Gain Control Block Amancay Thursday 23rd 11:50
18 Evaluation of de-embedding techniques for impedance characterization of magnetic nanoparticles Amancay Thursday 23rd 12:10
31 Impacto da Variabilidade PVT em Somadores na tecnologia FinFET Amancay Device variations - Resistitve Memories Thursday 23rd 13:30
34 PVT-Robust Ultra Low Voltage RC Filter Bulk-Driven Calibration Analysis Amancay Thursday 23rd 13:50
16 Análise das margens de ruído de diferentes topologias de células de memória SRAM de 1 bit Amancay Thursday 23rd 14:10
21 Avalia\c{c}\~ao da Robustez de Votadores Majoritários à Variabilidade PVT Amancay Thursday 23rd 14:30
8 Um Modelo Probabilístico para Cria\c{c}\~ao de PTMs de Portas L\'ogicas Combinacionais Amancay Thursday 23rd 14:50
2 A Symbolic Expression for the Area of the Memristor Characteristics and Power Considerations Amancay Thursday 23rd 15:10

Paper Presentations: PRIME

Number Title Room Session Day Time
5 A 280uW Sub-threshold Balun LNA for Medical Radio using Current Re-use Technique Amancay Analog Design Tuesday 21st 10:30
16 Grid-Voltage Sensorless Control of an LCL filter with Low Resonace Frequency Amancay Tuesday 21st 10:50
11 Design of a Delayless Feedback Path Free 2nd-order Two-Path Time-Interleaved Discrete-Time Delta-Sigma Modulator- a New Approach Amancay Tuesday 21st 11:10
26 HDL and Design Techniques Analysis for FPGA and ASIC Synthesis Amancay Tuesday 21st 11:30
27 Improved Lagrangian Relaxation-based Gate Size and VT Assignment for Very Large Circuits Amancay Tuesday 21st 11:50
28 Robustness Evaluation of FinFET Transistors under PVT Variability Amancay Tuesday 21st 12:10
17 Experimental Study of Progressive Breakdown in Different Conductance States of Resistive Switching Structures Amancay Devices and Digital Design Wednesday 22nd 10:30
15 Analyisis and Comparison of the CV-Dispersion of High-k, Bi-layered MOS InGaAs/InP stacks Amancay Wednesday 22nd 10:50
18 Synthesis and Design of a 4th Order Low-Pass DT Sigma-Delta Modulator in a 130nm CMOS process Amancay Wednesday 22nd 11:10
6 Proposal of a fuzzy logic controller for the improvement of irrigation scheduling decision-making in greenhouse horticulture. Amancay Wednesday 22nd 11:30
8 Programmable Assertion Checkers for Hardware Trojan Detection Amancay Wednesday 22nd 11:50
30 AES block cipher implementations with AMBA-AHB interface Amancay Wednesday 22nd 12:10